Solid-state image sensor and camera system

ABSTRACT

A solid-state image sensor including a pixel array portion formed from a two-dimensional array of ordinary imaging pixels each having a photoelectric conversion unit and configured to output an electric signal obtained through photoelectric conversion as a pixel signal, and focus detection pixels for detecting focus. The focus detection pixels include at least a first focus detection pixel and a second focus detection pixel each having a photoelectric conversion unit and configured to transfer and output an electric signal obtained through photoelectric conversion to an output node. The first focus detection pixel and the second focus detection pixel share the output node. The first focus detection pixel includes a first photoelectric conversion unit, and a first transfer gate for reading out an electron generated through photoelectric conversion in the first photoelectric conversion unit to the shared output node.

RELATED APPLICATION DATA

This application is a continuation of U.S. patent application Ser. No.14/579,378 filed Dec. 22, 2014, which is a continuation of U.S. patentapplication Ser. No. 13/747,183 filed Jan. 22, 2013, now U.S. Pat. No.8,964,084 issued Feb. 24, 2015, the entireties of which are incorporatedherein by reference to the extent permitted by law. The presentapplication claims the benefit of priority to Japanese PatentApplication No. JP 2012-018383 filed on Jan. 31, 2012 in the JapanPatent Office, the entirety of which is incorporated by reference hereinto the extent permitted by law.

BACKGROUND

The present technology relates to a solid-state image sensor,represented by a CMOS (complementary metal oxide semiconductor), onwhich ordinary imaging pixels and focus detection pixels aretwo-dimensionally arrayed, and a camera system.

An example of a known focus detection technology is pupil division phasedifference.

In a pupil division phase difference method, the amount of defocus of animaging lens is detected by dividing the light beams passing through theimaging lens to form a pair of divided images, and detecting patterndeviation between this pair of divided images.

A solid-state image sensor applying such a pupil division phasedifference method is described in, for example, JP 2008-103885A and JP2007-103590A.

The solid-state image sensor described in JP 2008-103885A is formed froma two-dimensional array of imaging pixels having a photoelectricconversion unit and focus detection pixels that have pairs of a firstphotoelectric conversion unit and a second photoelectric conversionunit.

Further, at an output unit, as illustrated in FIG. 1, a signal obtainedby adding the respective outputs from the first photoelectric conversionunits 11 and 21 of a first focus detection pixel 1 and a second focusdetection pixel 2 that are adjacent to each other is output from thefirst focus detection pixel 1. Similarly, a signal obtained by addingthe outputs from the second photoelectric conversion units 21 and 22 isoutput from the second focus detection pixel 2.

Namely, the solid-state image sensor described in JP 2008-103885A hastwo photoelectric conversion units for one focus detection pixel (AFpixel). Further, the charge signals from the photoelectric conversionunits forming a focus detection pair are added at a floating diffusionlayer, which is an output node.

The solid-state image sensor described in JP 2007-103590A is formed froma two-dimensional array of first pixel cells 3 as illustrated in FIG.2(A) and second pixel cells 4 as illustrated in FIG. 2(B).

The first pixel cells 3 include a first photoelectric conversion unit 31that generates charges based on incident light.

The second pixel cells 4 include an optical element (microlens) thatcollects incident light and second photoelectric conversion units 42 and43 that generate charges based on the light collected by the opticalelement.

A solid-state image sensor configured so that the focus detection pixelsare larger than the ordinary imaging pixels is also described in JP2007-127746.

SUMMARY

However, the above-described technologies suffer from the followingdrawbacks.

In the solid-state image sensor described in JP 2008-103885A, with alayout like that illustrated in FIG. 16 of JP 2008-103885A, the FDportion becomes larger. Consequently, conversion efficiencydeteriorates, and sensitivity during low illumination decreases, so thatlow illumination S/N is low. When there is a lot of so-called 1/f noise,for example, the detection accuracy at a low illumination decreases.

For such a solid-state image sensor, since an area that separates thephotoelectric conversion area (PD) is necessary in each focus detectionpixel, Qs is half or less that of an ordinary pixel.

Since it is necessary to prevent color mixing in the pulses byseparating the photoelectric conversion area (PD), a high-level fineprocess is necessary. Consequently, this technology is not suited topixel miniaturization.

Further, a potential design that is different for the ordinary pixelsand the focus detection pixels becomes necessary, so that the number ofsteps increases, which can even cause costs to increase.

In the solid-state image sensor described in JP 2007-103590A, for anexample of FD addition like that illustrated in FIG. 16 of JP2007-103590A, two transfer gates (85 and 86) have to be simultaneouslyon, and during focus detection, the drive method of the surroundingcircuits has to be separated from that of the ordinary drive.

Therefore, this technology is not suited to high-speed imaging.

Further, in this solid-state image sensor, since two pixels aresimultaneously read even for the ordinary pixels, the color of theordinary pixels are difficult to be differentiated.

Consequently, this technology suffers from the drawbacks of adeterioration in image quality and resolution.

Since the solid-state image sensor described in JP 2007-127746 hasportions that are far away from a transfer gate, this technology issusceptible to residual images.

Further, differences in the characteristics of the ordinary pixels andthe focus detection pixels tend to occur, and image deterioration due tothe fixed pattern noise of only the focus detection pixels can occur.

To avoid residual image defects, the voltage of the focus detectionpixel transfer gates has to be increased. However, this leads toincreased power consumption.

To avoid transfer defects, an implementation step to aid transfer has tobe added. However, this causes costs to increase.

If an implementation step is added to the focus detection pixels,process unevenness factors, such as alignment deviation, increase, sothat the characteristics tend to become uneven. This can lead todeterioration in image quality and yield.

According to an embodiment of the present technology, there is provideda solid-state image sensor, and a camera system, capable of improvingfocus detection accuracy during low illumination while suppressingdeterioration in image quality, deterioration in yield, increases inpower consumption, and increases in costs.

According to a first embodiment of the present disclosure, there isprovided a solid-state image sensor including a pixel array portionformed from a two-dimensional array of ordinary imaging pixels eachhaving a photoelectric conversion unit and configured to output anelectric signal obtained through photoelectric conversion as a pixelsignal, and focus detection pixels for detecting focus. The focusdetection pixels include at least a first focus detection pixel and asecond focus detection pixel each having a photoelectric conversion unitand configured to transfer and output an electric signal obtainedthrough photoelectric conversion to an output node. The first focusdetection pixel and the second focus detection pixel share the outputnode. The first focus detection pixel includes a first photoelectricconversion unit, and a first transfer gate for reading out an electrongenerated through photoelectric conversion in the first photoelectricconversion unit to the shared output node. The second focus detectionpixel includes a second photoelectric conversion unit, and a secondtransfer gate for reading out an electron generated throughphotoelectric conversion in the second photoelectric conversion unit tothe shared output node. The first transfer gate of the first focusdetection pixel and the second transfer gate of the second focusdetection pixel are electrically shared by a gate electrode to which acontrol signal for conduction control is applied.

According to a second embodiment of the present disclosure, there isprovided a camera system including a solid-state image sensor, anoptical unit configured to form an image of an object image on thesolid-state image sensor, and a signal processing unit configured toprocess an output signal from the solid-state image sensor, thesolid-state image sensor including a pixel array portion formed from atwo-dimensional array of ordinary imaging pixels each having aphotoelectric conversion unit and configured to output an electricsignal obtained through photoelectric conversion as a pixel signal, andfocus detection pixels for detecting focus. The focus detection pixelsinclude at least a first focus detection pixel and a second focusdetection pixel each having a photoelectric conversion unit andconfigured to transfer and output an electric signal obtained throughphotoelectric conversion to an output node. The first focus detectionpixel and the second focus detection pixel share the output node. Thefirst focus detection pixel includes a first photoelectric conversionunit, and a first transfer gate for reading out an electron generatedthrough photoelectric conversion in the first photoelectric conversionunit to the shared output node. The second focus detection pixelincludes a second photoelectric conversion unit, and a second transfergate for reading out an electron generated through photoelectricconversion in the second photoelectric conversion unit to the sharedoutput node. The first transfer gate of the first focus detection pixeland the second transfer gate of the second focus detection pixel areelectrically shared by a gate electrode to which a control signal forconduction control is applied.

According to an embodiment of the present technology, focus detectionaccuracy during low illumination can be improved while suppressingdeterioration in image quality, deterioration in yield, increases inpower consumption, and increases in costs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating the focus detection pixels disclosed inJP 2008-103885A;

FIG. 2 is a diagram illustrating the imaging pixels and the focusdetection pixels disclosed in JP 2007-103590A;

FIG. 3 is a diagram illustrating a configuration example of asolid-state image sensor according to an embodiment of the presenttechnology;

FIG. 4 is a diagram illustrating a configuration example of a pixelarray portion of a solid-state image sensor according to an embodimentof the present technology;

FIG. 5 is a diagram illustrating a configuration example of a circuit ofan imaging pixel and a focus detection pixel for a 2-pixel-sharing caseaccording to an embodiment of the present technology;

FIG. 6 is a diagram illustrating a configuration example of vertical2-pixel sharing as a first embodiment of the present technology;

FIG. 7 is a diagram illustrating a configuration example of a2-pixel-sharing transfer wire as a second embodiment of the presenttechnology, which illustrates a laminate structure of anFD-layer-sharing imaging pixel and focus detection pixel;

FIG. 8 is a diagram illustrating a configuration example of a2-pixel-sharing transfer wire as a second embodiment of the presenttechnology, which schematically illustrates a wire connection in thelaminate structure illustrated in FIG. 7;

FIG. 9 is a diagram schematically illustrating in a planar manner aconfiguration example of a 2-pixel-sharing transfer wire as a secondembodiment of the present technology, which schematically illustrates apixel pattern, which includes a first metal wire layer that is formedfrom a Si substrate, of an FD-layer-sharing imaging pixel and focusdetection pixel;

FIG. 10 is a diagram schematically illustrating in a planar manner aconfiguration example of a 2-pixel-sharing transfer wire as a secondembodiment of the present technology, which schematically illustrates apixel pattern including a first metal wire layer and a second metal wirelayer;

FIG. 11 is a diagram illustrating a 4-pixel-sharing pixel array exampleas a third embodiment of the present technology;

FIG. 12 is a diagram illustrating, for a 2-pixel-sharing case, a firstexample of a light shielding pattern of the focus detection pixelsarranged in a pixel array portion as a fourth embodiment of the presenttechnology;

FIG. 13 is a diagram illustrating, for a 2-pixel-sharing case, a secondexample of a light shielding pattern of the focus detection pixelsarranged in a pixel array portion as a fourth embodiment of the presenttechnology;

FIG. 14 is a diagram illustrating, for a 2-pixel-sharing case, a thirdexample of a light shielding pattern of the focus detection pixelsarranged in a pixel array portion as a fourth embodiment of the presenttechnology;

FIG. 15 is a series of diagrams illustrating, for a 2-pixel-sharingcase, a fourth example of a light shielding pattern of the focusdetection pixels arranged in a pixel array portion as a fourthembodiment of the present technology;

FIG. 16 is a diagram illustrating, for a 4-pixel-sharing case, a firstexample of a light shielding pattern of the focus detection pixelsarranged in a pixel array portion as a fourth embodiment of the presenttechnology;

FIG. 17 is a diagram illustrating, for a 4-pixel-sharing case, a secondexample of a light shielding pattern of the focus detection pixelsarranged in a pixel array portion as a fourth embodiment of the presenttechnology;

FIG. 18 is a diagram illustrating, for a 2-pixel-sharing case, anexample of a pixel array pattern in which there is no color filter inthe overall structure as a fifth embodiment of the present technology;

FIG. 19 is a diagram illustrating, for a 2-pixel-sharing case, anexample of a pixel array pattern in which a color filter is provided inthe overall structure, but not for the focus detection pixels, as afifth embodiment of the present technology;

FIG. 20 is a diagram illustrating, for a 2-pixel-sharing case, anexample of a pixel array pattern in which a color filter is provided inthe overall structure, and is also arranged for the focus detectionpixels, as a fifth embodiment of the present technology;

FIG. 21 is a diagram illustrating, for a 2-pixel-sharing case, anexample of a pixel array pattern in which a color filter is provided inthe overall structure, and is also arranged for a part of the focusdetection pixels, as a fifth embodiment of the present technology;

FIG. 22 is a diagram illustrating a first example of a horizontal2-pixel-sharing pixel array as a sixth embodiment of the presenttechnology;

FIG. 23 is a diagram illustrating a second example of a horizontal2-pixel-sharing pixel array as a sixth embodiment of the presenttechnology;

FIG. 24 is a diagram illustrating a third example of a horizontal2-pixel-sharing pixel array as a sixth embodiment of the presenttechnology;

FIG. 25 is a diagram illustrating a fourth example of a horizontal2-pixel-sharing pixel array as a sixth embodiment of the presenttechnology;

FIG. 26 is series of diagrams illustrating, for a horizontal2-pixel-sharing case, an example of a light shielding pattern of thefocus detection pixels arranged in a pixel array portion as a sixthembodiment of the present technology; and

FIG. 27 is a diagram illustrating an example of a configuration of acamera system in which the solid-state image sensor according to anembodiment of the present technology is applied.

DETAILED DESCRIPTION OF THE EMBODIMENT(S)

Hereinafter, preferred embodiments of the present disclosure will bedescribed in detail with reference to the appended drawings. Note that,in this specification and the appended drawings, structural elementsthat have substantially the same function and structure are denoted withthe same reference numerals, and repeated explanation of thesestructural elements is omitted.

Embodiments of the present technology will now be described withreference to the drawings. The description will be made in the followingorder: 1. Overall schematic configuration of a solid-state image sensor;2. First embodiment (configuration example of vertical 2-pixel sharing;3. Second embodiment (configuration example of a 2-pixel-sharingtransfer wire; 4. Third embodiment (example of a 4-pixel-sharing pixelarray; 5. Fourth embodiment (example of focus detection pixel lightshielding patterns); 6. Fifth embodiment (configuration example of focusdetection pixels associated with a color filter); 7. Sixth embodiment(configuration example of horizontal 2-pixel sharing; and 8.Configuration example of a camera system.

1. Overall Schematic Configuration of a Solid-State Image Sensor

FIG. 3 is a diagram illustrating a configuration example of asolid-state image sensor according to an embodiment of the presenttechnology.

FIG. 4 is a diagram illustrating a configuration example of a pixelarray portion in a solid-state image sensor according to an embodimentof the present technology.

In the following embodiment of the present technology, a CMOS sensorwill be described as an example of a solid-state image sensor.

A solid-state image sensor 100 includes a pixel array portion 110, a rowselection circuit (Vdec) 120, and a column read circuit (AFE) 130.

A pixel signal read unit is formed by the row selection circuit 120 andthe column read circuit 130.

The pixel array portion 110 is formed from a plurality of pixel circuitsarrayed in two-dimensions (in a matrix) of M rows×N columns.

Specifically, as illustrated in FIG. 4, the pixel array portion 110 isformed from a two-dimensional array of a mixture of ordinary imagingpixels 200 having a photoelectric conversion unit and focus detectionpixels (AF pixels) 300 having a photoelectric conversion unit.

The pixel array portion 110 according to an embodiment of the presenttechnology has a configuration in which a floating diffusion (FD) layeris shared as an output node between two adjacent imaging pixels 200.FIG. 4 illustrates a configuration example in which two imaging pixels200 adjacent in a perpendicular direction share an FD layer as an outputnode.

Similarly, the pixel array portion 110 according to an embodiment of thepresent technology has a configuration in which two adjacent focusdetection pixels 300 share an FD layer as an output node. Similar to theimaging pixels, FIG. 4 illustrates a configuration example in which twofocus detection pixels 300 adjacent in a perpendicular direction sharean FD layer as an output node.

A first focus detection pixel 300-1 and a second focus detection pixel300-2 that share an FD layer have a first transfer gate AFTRG1 and asecond transfer gate AFTRG2, respectively, for reading the electrons(charges) produced by photoelectric conversion in a photoelectricconversion unit PD.

The first transfer gate AFTRG1 and second transfer gate AFTRG2 areelectrically connected (shared).

In other words, the first transfer gate AFTRG1 and second transfer gateAFTRG2 are controlled to be simultaneously turned on and off in parallelby the same transfer control signal TR.

Further, each of the focus detection pixels 300 are configured so that,for example, roughly half of the area where light is incident on thephotoelectric conversion unit is shielded by a light shielding portionLC.

The first focus detection pixel 300-1 and the second focus detectionpixel 300-2 sharing an FD layer have the same aperture size.

Further, the ordinary imaging pixels 200 are configured so that eventhough a part of the area where light is incident on the photoelectricconversion unit is shielded, the light incident area is larger than thatof the focus detection pixels 300. In other words, the imaging pixels200 have a larger aperture size than the aperture size of the focusdetection pixels.

However, according to an embodiment of the present technology, theordinary imaging pixels 200 and the focus detection pixels 300 may havethe same pixel size.

Various modes of the light shielded site are possible for the focusdetection pixels 300.

The example illustrated in FIG. 4 illustrates, as viewed from the front,a right light-shielded focus detection pixel 300-R, in which a portionon the right side (a first edge portion) of a focus detection pixel 300forming a rectangular shape is shielded, and a left light-shielded focusdetection pixel 300-L, in which a portion on the left side (a secondedge portion) is shielded.

In addition, the example illustrated in FIG. 4 also shows an upperlight-shielded focus detection pixel 300-U, in which a portion on theupper side (a third edge portion) of a focus detection pixel 300 isshielded, and a bottom light-shielded focus detection pixel 300-B, inwhich a portion on the lower side (a fourth edge portion) is shielded.

In FIG. 4, to simplify the diagram, a 4×4 pixel array is illustrated. Inthe pixel array illustrated in FIG. 4, the imaging pixels 200 and focusdetection pixels 300 are arranged as follows.

[Pixel Array Example]

In the first row, a right light-shielded focus detection pixel 300R-11is arranged in the first column, a left light-shielded focus detectionpixel 300L-12 is arranged in the second column, an ordinary imagingpixel 200-13 is arranged in the third column, an upper light-shieldedfocus detection pixel 300U-14 is arranged in the fourth column, and abottom light-shielded focus detection pixel 300L-15 is arranged in thefifth column.

In the second row, a right light-shielded focus detection pixel 300R-21is arranged in the first column, a left light-shielded focus detectionpixel 300L-22 is arranged in the second column, an ordinary imagingpixel 200-23 is arranged in the third column, an upper light-shieldedfocus detection pixel 300U-24 is arranged in the fourth column, and abottom light-shielded focus detection pixel 300L-25 is arranged in thefifth column.

In the third row, an ordinary imaging pixel 200-31 is arranged in thefirst column, an imaging pixel 200-32 is arranged in the second column,an imaging pixel 200-33 is arranged in the third column, an imagingpixel 200-34 is arranged in the fourth column, and an imaging pixel200-35 is arranged in the fifth column.

In the fourth row, an ordinary imaging pixel 200-41 is arranged in thefirst column, an imaging pixel 200-42 is arranged in the second column,an imaging pixel 200-43 is arranged in the third column, an imagingpixel 200-44 is arranged in the fourth column, and an imaging pixel200-45 is arranged in the fifth column.

In the example illustrated in FIG. 4, the right light-shielded firstfocus detection pixel 300R-11 of the first row, first column and theright light-shielded second focus detection pixel 300R-21 of the secondrow, first column share a floating diffusion layer FDC11 as an outputnode. Further, the first focus detection pixel 300R-11 and the secondfocus detection pixel 300R-21 also share a reset transistor TRST, anamplification transistor TAMP, and a selection transistor TSEL.

The first focus detection pixel 300R-11 has a first transfer gateAFTRG11, and the second focus detection pixel 300R-21 has a secondtransfer gate AFTRG21.

The first transfer gate AFTRG11 and the second transfer gate AFTRG21 areelectrically connected by a connection electrode CEL11.

Further, the connection electrode CEL11 connecting the first transfergate AFTRG11 and the second transfer gate AFTRG21 is connected to atransfer control line LTR1 along which a transfer control signal TR1 iscarried.

Consequently, the first transfer gate AFTRG11 and the second transfergate AFTRG21 are controlled to be simultaneously turned on and off inparallel by the same transfer control signal TR1.

The left light-shielded first focus detection pixel 300L-12 of the firstrow, second column and the left light-shielded second focus detectionpixel 300L-22 of the second row, second column share a floatingdiffusion layer FDC 12 as an output node. Further, the first focusdetection pixel 300L-12 and the second focus detection pixel 300L-22also share a reset transistor TRST, an amplification transistor TAMP,and a selection transistor TSEL.

The first focus detection pixel 300L-12 has a first transfer gateAFTRG12, and the second focus detection pixel 300L-22 has a secondtransfer gate AFTRG22.

The first transfer gate AFTRG12 and the second transfer gate AFTRG22 areelectrically connected by a connection electrode CEL12.

Further, the connection electrode CEL12 connecting the first transfergate AFTRG12 and the second transfer gate AFTRG22 is connected to thetransfer control line LTR1 along which the transfer control signal TR1is carried.

Consequently, the first transfer gate AFTRG12 and the second transfergate AFTRG22 are controlled to be simultaneously turned on and off inparallel by the same transfer control signal TR1.

The first imaging pixel 200-13 of the first row, third column and thesecond imaging pixel 200-23 of the second row, third column share afloating diffusion layer FDC13 as an output node. Further, the firstimaging pixel 200-13 and the second imaging pixel 200-23 also share areset transistor TRST, an amplification transistor TAMP, and a selectiontransistor TSEL.

The first imaging pixel 200-13 has a first transfer gate TRG13, and thesecond imaging pixel 200-23 has a second transfer gate TRG23.

The first transfer gate TRG13 is connected to the transfer control lineLTR1 along which the transfer control signal TR1 is carried.

The second transfer gate TRG23 is connected to a transfer control lineLTR2 along which a transfer control signal TR2 is carried.

Consequently, the first transfer gate TRG13 and the second transfer gateTRG23 are controlled to be individually turned on and off by differenttransfer control signals TR1 and TR2.

The upper light-shielded first focus detection pixel 300U-14 of thefirst row, fourth column and the upper light-shielded second focusdetection pixel 300U-24 of the second row, fourth column share afloating diffusion layer FDC14 as an output node. Further, the firstfocus detection pixel 300U-14 and the second focus detection pixel300U-24 also share a reset transistor TRST, an amplification transistorTAMP, and a selection transistor TSEL.

The first focus detection pixel 300U-14 has a first transfer gateAFTRG14, and the second focus detection pixel 300U-24 has a secondtransfer gate AFTRG24.

The first transfer gate AFTRG14 and the second transfer gate AFTRG24 areelectrically connected by a connection electrode CEL14.

Further, the connection electrode CEL14 connecting the first transfergate AFTRG14 and the second transfer gate AFTRG24 is connected to thetransfer control line LTR1 along which the transfer control signal TR1is carried.

Consequently, the first transfer gate AFTRG14 and the second transfergate AFTRG24 are controlled to be simultaneously turned on and off inparallel by the same transfer control signal TR1.

The bottom light-shielded first focus detection pixel 300B-15 of thefirst row, fifth column and the bottom light-shielded second focusdetection pixel 300B-25 of the second row, fifth column share a floatingdiffusion layer FDC15 as an output node. Further, the first focusdetection pixel 300B-15 and the second focus detection pixel 300B-25also share a reset transistor TRST, an amplification transistor TAMP,and a selection transistor TSEL.

The first focus detection pixel 300B-15 has a first transfer gateAFTRG15, and the second focus detection pixel 300B-25 has a secondtransfer gate AFTRG25.

The first transfer gate AFTRG15 and the second transfer gate AFTRG25 areelectrically connected by a connection electrode CEL15.

Further, the connection electrode CEL15 connecting the first transfergate AFTRG15 and the second transfer gate AFTRG25 is connected to thetransfer control line LTR1 along which the transfer control signal TR1is carried.

Consequently, the first transfer gate AFTRG15 and the second transfergate AFTRG25 are controlled to be simultaneously turned on and off inparallel by the same transfer control signal TR1.

The first imaging pixel 200-31 of the third row, first column and thesecond imaging pixel 200-41 of the fourth row, first column share afloating diffusion layer FDC31 as an output node. Further, the firstimaging pixel 200-31 and the second imaging pixel 200-41 also share areset transistor TRST, an amplification transistor TAMP, and a selectiontransistor TSEL.

The first imaging pixel 200-31 has a first transfer gate TRG31, and thesecond imaging pixel 200-41 has a second transfer gate TRG41.

The first transfer gate TRG31 is connected to a transfer control lineLTR3 along which a transfer control signal TR3 is carried.

The second transfer gate TRG41 is connected to a transfer control lineLTR4 along which a transfer control signal TR4 is carried.

Consequently, the first transfer gate TRG31 and the second transfer gateTRG41 are controlled to be individually turned on and off by differenttransfer control signals TR3 and TR4.

The first imaging pixel 200-32 of the third row, second column and thesecond imaging pixel 200-42 of the fourth row, second column share afloating diffusion layer FDC32 as an output node. Further, the firstimaging pixel 200-32 and the second imaging pixel 200-42 also share areset transistor TRST, an amplification transistor TAMP, and a selectiontransistor TSEL.

The first imaging pixel 200-32 has a first transfer gate TRG32, and thesecond imaging pixel 200-42 has a second transfer gate TRG42.

The first transfer gate TRG32 is connected to the transfer control lineLTR3 along which the transfer control signal TR3 is carried.

The second transfer gate TRG42 is connected to the transfer control lineLTR4 along which the transfer control signal TR4 is carried.

Consequently, the first transfer gate TRG32 and the second transfer gateTRG42 are controlled to be individually turned on and off by differenttransfer control signals TR3 and TR4.

The first imaging pixel 200-33 of the third row, third column and thesecond imaging pixel 200-43 of the fourth row, third column share afloating diffusion layer FDC33 as an output node. Further, the firstimaging pixel 200-33 and the second imaging pixel 200-43 also share areset transistor TRST, an amplification transistor TAMP, and a selectiontransistor TSEL.

The first imaging pixel 200-33 has a first transfer gate TRG33, and thesecond imaging pixel 200-43 has a second transfer gate TRG43.

The first transfer gate TRG33 is connected to the transfer control lineLTR3 along which the transfer control signal TR3 is carried.

The second transfer gate TRG43 is connected to the transfer control lineLTR4 along which the transfer control signal TR4 is carried.

Consequently, the first transfer gate TRG33 and the second transfer gateTRG43 are controlled to be individually turned on and off by differenttransfer control signals TR3 and TR4.

The first imaging pixel 200-34 of the third row, fourth column and thesecond imaging pixel 200-44 of the fourth row, fourth column share afloating diffusion layer FDC34 as an output node. Further, the firstimaging pixel 200-34 and the second imaging pixel 200-44 also share areset transistor TRST, an amplification transistor TAMP, and a selectiontransistor TSEL.

The first imaging pixel 200-34 has a first transfer gate TRG34, and thesecond imaging pixel 200-44 has a second transfer gate TRG44.

The first transfer gate TRG34 is connected to the transfer control lineLTR3 along which the transfer control signal TR3 is carried.

The second transfer gate TRG44 is connected to the transfer control lineLTR4 along which the transfer control signal TR4 is carried.

Consequently, the first transfer gate TRG34 and the second transfer gateTRG44 are controlled to be individually turned on and off by differenttransfer control signals TR3 and TR4.

The first imaging pixel 200-35 of the third row, fifth column and thesecond imaging pixel 200-45 of the fourth row, fifth column share afloating diffusion layer FDC35 as an output node. Further, the firstimaging pixel 200-35 and the second imaging pixel 200-45 also share areset transistor TRST, an amplification transistor TAMP, and a selectiontransistor TSEL.

The first imaging pixel 200-35 has a first transfer gate TRG35, and thesecond imaging pixel 200-45 has a second transfer gate TRG45.

The first transfer gate TRG35 is connected to the transfer control lineLTR3 along which the transfer control signal TR3 is carried.

The second transfer gate TRG45 is connected to the transfer control lineLTR4 along which the transfer control signal TR4 is carried.

Consequently, the first transfer gate TRG35 and the second transfer gateTRG45 are controlled to be individually turned on and off by differenttransfer control signals TR3 and TR4.

[Circuit Configuration Example of 2-Pixel-Sharing Imaging Pixels andFocus Detection Pixels]

Next, a configuration example of a circuit of an imaging pixel and afocus detection pixel for a 2-pixel-sharing case will be described.

FIG. 5 is a diagram illustrating a configuration example of a circuit ofan imaging pixel and a focus detection pixel for a 2-pixel-sharing caseaccording to an embodiment of the present technology.

FIG. 5 illustrates an example of the pixels in a CMOS image sensorbasically configured from four transistors.

A 2-pixel-sharing imaging pixel 200A has a photodiode (PD) 211-1 as aphotoelectric conversion unit of a first imaging pixel 200A-1 and atransfer transistor 212-1 as a transfer gate.

The imaging pixel 200A has a photodiode (PD) 211-2 as a photoelectricconversion unit of a second imaging pixel 200A-2 and a transfertransistor 212-2 as a transfer gate.

The imaging pixel 200A has a floating diffusion layer FDC1 as an outputnode that is shared by the first imaging pixel 200A-1 and the secondimaging pixel 200A-2.

The imaging pixel 200A also has a reset transistor (TRST) 213, anamplification transistor (TAMP) 214, and a selection transistor (TSEL)215.

The photodiodes 211-1 and 211-2 photoelectrically convert incident lightinto charges (here, electrons) based on the amount of incident light.

At the first imaging pixel 200A-1, the transfer transistor 212-1 as atransfer element (transfer gate) is connected between the photodiode211-1 and the floating diffusion layer FDC1 as an output node. Atransfer control signal TR1 is applied to the gate (transfer gate) ofthe transfer transistor 212-1 via the transfer control line LTR1.

Consequently, the transfer transistor 212-1 transfers the electronsphotoelectrically converted by the photodiode 211-1 to the floatingdiffusion layer FDC1.

At the second imaging pixel 200A-2, the transfer transistor 212-2 as atransfer element (transfer gate) is connected between the photodiode211-2 and the floating diffusion layer FDC1 as an output node. Atransfer control signal TR2 is applied to the gate (transfer gate) ofthe transfer transistor 212-2 via the transfer control line LTR2.

Consequently, the transfer transistor 212-2 transfers the electronsphotoelectrically converted by the photodiode 211-2 to the floatingdiffusion layer FDC1.

The reset transistor 213 is connected between a power supply line LVDD,which a power supply voltage VDD is supplied to, and the floatingdiffusion layer FDC1. A reset signal RST is applied to the gate of thereset transistor via a reset control line LRST.

Consequently, the reset transistor 213 as a reset element resets theelectric potential of the floating diffusion layer FDC1 to the electricpotential of the power supply line LVDD.

A gate of the amplification transistor 214 acting as an amplificationelement is connected to the floating diffusion layer FDC1. Namely, thefloating diffusion layer FDC1 can also function as an input node of theamplification transistor 214 acting as an amplification element.

The amplification transistor 214 and the selection transistor 215 areconnected in series between the power supply line LVDD to which a powersupply voltage VDD is supplied and a signal line LSGN1.

Thus, the amplification transistor 214 is connected to the signal lineLSGN1 via the selection transistor 215, thereby configuring a constantcurrent source external to the pixel portion and a source follower.

Further, the selection transistor 215 is turned on when a selectionsignal SEL, which is a control signal based on an address signal, isapplied to the selection transistor 215 gate via the selection controlline LSEL.

When the selection transistor 215 is tuned on, the amplificationtransistor 214 amplifies the electric potential of the floatingdiffusion layer FDC1, and outputs a voltage based on that amplifiedelectric potential to a signal line LSGL1. The voltage VSL1 output fromeach pixel is output to the column read circuit 130 via the signal lineLSGL1.

These operations are simultaneously performed for each pixel in 12 rowsof pixels, because, for example, the respective gates of the transfertransistors 212-1 and 212-2, the reset transistor 213, and the selectiontransistor 215 are connected in row units.

A 2-pixel-sharing focus detection pixel 300A has a photodiode (PD) 311-1as a photoelectric conversion unit of a first focus detection pixel300A-1 and a transfer transistor 312-1 as a transfer gate.

The focus detection pixel 300A has a photodiode (PD) 311-2 as aphotoelectric conversion unit of a second focus detection pixel 300A-2and a transfer transistor 312-2 as a transfer gate.

The focus detection pixel 300A has a floating diffusion layer FDC2 as anoutput node that is shared by the first focus detection pixel 300A-1 andthe second focus detection pixel 300A-2.

The focus detection pixel 300A also has a reset transistor (TRST) 313,an amplification transistor (TAMP) 314, and a selection transistor(TSEL) 315.

The photodiodes 311-1 and 311-2 photoelectrically convert incident lightinto charges (here, electrons) based on the amount of incident light.

At the first focus detection pixel 300A-1, the transfer transistor 312-1as a transfer element (transfer gate) is connected between thephotodiode 311-1 and the floating diffusion layer FDC2 as an outputnode. The transfer control signal TR1 is applied to the gate (transfergate) of the transfer transistor 312-1 via the transfer control lineLTR1.

Consequently, the transfer transistor 312-1 transfers the electronsphotoelectrically converted by the photodiode 311-1 to the floatingdiffusion layer FDC2.

At the second focus detection pixel 300A-2, the transfer transistor312-2 as a transfer element (transfer gate) is connected between thephotodiode 311-2 and the floating diffusion layer FDC2 as an outputnode. The transfer control signal TR1 is applied to the gate (transfergate) of the transfer transistor 312-2 via the transfer control lineLTR1.

Consequently, the transfer transistor 312-2 transfers the electronsphotoelectrically converted by the photodiode 311-2 to the floatingdiffusion layer FDC2.

The reset transistor 313 is connected between a power supply line LVDD,which a power supply voltage VDD is supplied to, and the floatingdiffusion layer FDC2. A reset signal RST is applied to the gate of thereset transistor via a reset control line LRST.

Consequently, the reset transistor 313 as a reset element resets theelectric potential of the floating diffusion layer FDC2 to the electricpotential of the power supply line LVDD.

A gate of the amplification transistor 314 acting as an amplificationelement is connected to the floating diffusion layer FDC2. Namely, thefloating diffusion layer FDC2 can also function as an input node of theamplification transistor 314 acting as an amplification element.

The amplification transistor 314 and the selection transistor 315 areconnected in series between the power supply line LVDD to which a powersupply voltage VDD is supplied and a signal line LSGN2.

Thus, the amplification transistor 214 is connected to a signal lineLSGN2 via the selection transistor 315, thereby configuring a constantcurrent source external to the pixel portion and a source follower.

Further, the selection transistor 315 is turned on when the selectionsignal SEL, which is a control signal based on an address signal, isapplied to the selection transistor 315 gate via the selection controlline LSEL.

When the selection transistor 315 is tuned on, the amplificationtransistor 314 amplifies the electric potential of the floatingdiffusion layer FDC2, and outputs a voltage based on that amplifiedelectric potential to a signal line LSGL2. The voltage VSL2 output fromeach pixel is output to the column read circuit 130 via the signal lineLSGL2.

These operations are simultaneously performed for each pixel in 2 rowsworth of focus detection pixels, because, for example, the respectivegates of the transfer transistors 312-1 and 312-2, the reset transistor313, and the selection transistor 315 are connected in row units.

The reset control line LRST, the transfer control line LTR, and theselection control line LSEL wired in the pixel array portion 110 arewired as a set in each row unit of the pixel array.

M number of the LRST, LTRG, and LSEL control lines are provided,respectively.

The reset control line LRST, the transfer control line LTR, and theselection control line LSEL are driven by the row selection circuit 120.

The row selection circuit 120 controls operation of the pixels arrangedin an arbitrary row among the pixel array portion 110. The row selectioncircuit 120 controls the pixels via the control lines LRST, LTRG, andLSEL.

The column read circuit 130 receives via the signal output line LSGN thedata of a pixel row read and controlled by the row selection circuit120, and transfers the received data to a latter-stage signal processingcircuit.

The column read circuit 130 can also include a CDS (correlated doublesampling) circuit and an ADC (analog digital converter).

As described above, the solid-state image sensor 100 according to anembodiment of the present technology includes a pair of phase differencefocus detection pixels (AF pixels) 300A-1 and 300A-2.

The pair of first and second focus detection pixels 300A-1 and 300A-2share the floating diffusion layer FDC2, and are configured so that thegates of the transfer transistors 312-1 and 312-2 acting as transfergates are connected to a shared transfer control line LTR1.

Therefore, when an ON pulse is input to one transfer control line LTR1,the two pixels simultaneously turn on the transfer transistors 312-1 and312-2 acting as transfer gates.

Consequently, the electrons accumulated in the photodiode 311-1 of thefirst focus detection pixel 300A-1 and the electrons accumulated in thephotodiode 311-2 of the second focus detection pixel 300A-2 aretransferred simultaneously and in parallel to the floating diffusionlayer FDC2.

Further, these electrons are added up as a signal by the floatingdiffusion layer FDC2.

Consequently, the signal level (sensitivity) of the focus detectionpixels improves, so that focus detection accuracy during lowillumination can be improved.

Since the photoelectric conversion unit (PD unit) of the focus detectionpixels 300 can be configured with the same layout as the ordinaryimaging pixels 200, compared with the problems (miniaturization) thatcan occur in JP 2008-103885A, the present technology can achieve betterminiaturization and is more advantageous.

Further, in this embodiment of the present technology, since the focusdetection pixels are subjected to FD addition based on an ordinarydriving method, there is no need to change the drive method for the FDaddition of the focus detection pixels.

Further, since the ordinary imaging pixels 200 are wired and connectedin a typical manner, the imaging pixels can be read row by row.

An example was described above of the overall schematic configuration,pixel array, and 2-pixel-sharing imaging pixel and focus detection pixelcircuit configuration of the solid-state image sensor 100 according toan embodiment of the present technology.

Although some parts will overlap, specific examples of a pixel sharingconfiguration that can be applied to the present technology, lightshielding of the focus detection pixels, provision of a color filter,pixel arrays and the like will now be described as first to sixthembodiments.

2. First Embodiment

FIGS. 6(A) and 6(B) are diagrams illustrating a configuration example ofvertical 2-pixel-sharing as a first embodiment of the presenttechnology.

FIG. 6(A) illustrates a vertical 2-pixel-sharing pattern of ordinaryimaging pixels, and FIG. 6(B) illustrates a vertical 2-pixel-sharingpattern of focus detection pixels.

The first embodiment illustrated in FIG. 6 illustrates a configurationof a vertical 2-pixel-sharing pattern that has the same pixel array asdescribed with reference to FIG. 4. For ease of understanding, partsthat are the same as in FIG. 4 are represented using the same referencenumerals.

In FIG. 6, the photodiode (PD) photoelectric conversion unit, thefloating diffusion layer FD, the gate electrodes, and the transfercontrol line LTR wires are simply illustrated.

Further, although for convenience the contacts connecting the FD layersand the wires are not illustrated, in order for the FD portions to bereset, the FD portions are electrically connected to the source side ofthe reset transistor TRST.

As illustrated in FIGS. 6(A) and 6(B), the solid-state image sensor 100is configured so that the transfer gates AFTG1 and AFTG2 are shared by,among the imaging pixels 200 and focus detection pixels 300, only thepair of first and second focus detection pixels 300-1 and 300-2.

Namely, the first focus detection pixel 300-1 and the second focusdetection pixel 300-2 share a floating diffusion layer FD, and share agate electrode of the first and second transfer gates (transistors) thattransfer the accumulated electrons in the photoelectric conversion unitsPD to the FD layer.

Specifically, the first transfer gate of the first focus detection pixel300-1 and the second transfer gate of the second focus detection pixel300-2 are controlled to be simultaneously turned on and off in parallelby a shared transfer control signal TR1.

For example, at a high level, the transfer control signal TR1 turns thetwo transfer gates on, so that the electrons accumulated in thephotoelectric conversion units PD of the pair of the first focusdetection pixel 300-1 and the second focus detection pixel 300-2 aretransferred to a shared FD layer, and subjected to FD addition.

Consequently, a signal level similar to the ordinary imaging pixels200-1 and 200-2 can be obtained.

The ordinary imaging pixels 200 are configured so that a floatingdiffusion layer FD is shared between two adjacent pixels, but thetransfer gate (transistor) gate electrodes are individually formed.

Namely, the first transfer gate of the first focus detection pixel 300-1and the second transfer gate of the second focus detection pixel 300-2are controlled to be individually turned on and off by differenttransfer control signals TR1 and TR2.

Therefore, the signals from each of the imaging pixels 200 can beindividually read.

3. Second Embodiment

FIGS. 7 and 8 are diagrams illustrating a configuration example of a2-pixel-sharing transfer wire as a second embodiment of the presenttechnology.

FIG. 7 illustrates a laminate structure of an FD-layer-sharing imagingpixel and focus detection pixel. FIG. 8 schematically illustrates a wireconnection in the laminate structure illustrated in FIG. 7.

Focus detection pixels 300-1 and 300-2 are configured so thatphotoelectric conversion units PD321 and PD322, transfer gates AFTRG321and AFTRG322, and a shared floating diffusion layer FD321 are formed ona semiconductor substrate (silicon substrate) 321.

The transfer gates AFTRG321 and AFTRG322 are raised by a contact CT321and connected to an intermediate electrode layer 322, which is a firstmetal layer of an upper layer.

This intermediate electrode layer 322 is itself raised by a contactCT322 and connected to a transfer control line LTRG1 that is formed froma second metal layer 323 of an upper layer.

In this example, the intermediate electrode layer 322 is not connectedto the transfer control line LTR2, which is formed from a second metallayer 324 for the transfer control signal TR2.

Even in this configuration, the pair of first and second focus detectionpixels 300-1 and 300-2 is only subject to one transfer control signalTR1, so that when the transfer control signal TR1 is at a high level,the two transfer gates are turned on.

Consequently, the electrons accumulated in the photoelectric conversionunits PD321 and PD322 of the pair of the first focus detection pixel300-1 and the second focus detection pixel 300-2 are transferred to ashared FD layer, and subjected to FD addition.

As a result, a signal level similar to the ordinary imaging pixels 200-1and 200-2 can be obtained.

FIGS. 9 and 10 are diagrams schematically illustrating in a planarmanner a configuration example of a 2-pixel-sharing transfer wire as asecond embodiment of the present technology.

FIG. 9 schematically illustrates a pixel pattern, which includes a firstmetal wire layer that is formed from a Si substrate, of anFD-layer-sharing imaging pixel and focus detection pixel. FIG. 10schematically illustrates a pixel pattern including a first metal wirelayer and a second metal wire layer.

In FIGS. 9 and 10, for convenience the contacts connecting the FD layersand the wires are not illustrated.

As illustrated in FIG. 9, at the focus detection pixels 300-1 and 300-2,light shielding portions LC321 and LC322 for shielding the lightincident on the photoelectric conversion units PD321 and PD322 areformed from a metal in the same layer as the intermediate electrodelayer 322, which is a first metal layer.

In this example, the light shielding portions LC321 and LC322 are formedso as to shield roughly half of the area where light is incident on thephotoelectric conversion units PD321 and PD322. This example illustratesleft shielded light as an example.

Therefore, the ordinary imaging pixels 200-1 and 200-2 are configured sothat even though a part of the area where light is incident on thephotoelectric conversion unit is shielded, the light incident area islarger than that of the focus detection pixels 300-1 and 300-2. In otherwords, the imaging pixels 200 have a larger aperture size than theaperture size of the focus detection pixels.

However, in this embodiment of the present technology, the ordinaryimaging pixels 200 and the focus detection pixels 300 have the samepixel size.

Further, as illustrated in FIGS. 9 and 10, the transfer gates and thefirst metal wire layer are connected by a contact (via) CT321, and thefirst metal wire layer and the second metal layer are connected by acontact CT322.

4. Third Embodiment

FIG. 11 is a diagram illustrating a 4-pixel-sharing pixel array exampleas a third embodiment of the present technology.

FIG. 11 illustrates a 2×2-pixel-sharing (4-pixel unit) case.

Ordinary imaging pixels 200-1 to 200-4, which include photoelectricconversion units PD221 to PD224, are configured so that when a pulse isinput in the order of TR1→TR2→TR3→TR4 to the transfer control linesLTR1, LTR2, LTR3, and LTR4, transfer gates TRG1 to TRG4 are turnedon/off in order.

Based on this operation, the signals from the pixels can be read pixelby pixel.

In the example illustrated in FIG. 11, the focus detection pixels 300-1to 300-4 are configured so that the transfer gate is connected to onlythe transfer control line LTR2.

When a pulse as the transfer control signal TR2 is applied to thetransfer control line LTR2, the transfer gates of the four (2×2) focusdetection pixels 300-1 to 300-4 are simultaneously turned on, and fourpixels worth of signals is added by the floating diffusion layer FD.

5. Fourth Embodiment

FIG. 12 is a diagram illustrating, for a 2-pixel-sharing case, a firstexample of a light shielding pattern of the focus detection pixelsarranged in a pixel array portion as a fourth embodiment of the presenttechnology.

FIG. 12 illustrates an example in which left and right light-shieldedfocus detection pixels 300 are arranged on a part of a pixel arrayportion 110B.

In this example, left light-shielded, vertical 2-pixel-sharing focusdetection pixels 300L-1 and 300L-2 and right light-shielded, vertical2-pixel-sharing focus detection pixels 300R-1 and 300R-2 are alternatelyarranged.

Further, although FIG. 12 is illustrated as if there are focus detectionpixels consecutively arranged in the horizontal direction in thediagram, the focus detection pixels do not have to be consecutivelyarranged. For example, as illustrated in FIG. 4, ordinary imaging pixelsmay be arranged in between.

FIG. 13 is a diagram illustrating, for a 2-pixel-sharing case, a secondexample of a light shielding pattern of the focus detection pixelsarranged in a pixel array portion as a fourth embodiment of the presenttechnology.

FIG. 13 illustrates an example in which upper and bottom light-shieldedfocus detection pixels 300 are arranged on a part of a pixel arrayportion 110C.

In this example, upper light-shielded, vertical 2-pixel-sharing focusdetection pixels 300U-1 and 300U-2 and bottom light-shielded, vertical2-pixel-sharing focus detection pixels 300B-1 and 300B-2 are alternatelyarranged.

Further, although FIG. 13 is illustrated as if there are focus detectionpixels consecutively arranged in the horizontal direction in thediagram, the focus detection pixels do not have to be consecutivelyarranged. For example, as illustrated in FIG. 4, ordinary imaging pixelsmay be arranged in between.

FIG. 14 is a diagram illustrating, for a 2-pixel-sharing case, a thirdexample of a light shielding pattern of the focus detection pixelsarranged in a pixel array portion as a fourth embodiment of the presenttechnology.

FIG. 14 illustrates an example in which upper and bottom light-shieldedfocus detection pixels 300 are arranged on a part of a pixel arrayportion 110D.

In this example, right light-shielded, vertical 2-pixel-sharing focusdetection pixels 300R-1 and 300R-2 and left light-shielded, vertical2-pixel-sharing focus detection pixels 300L-1 and 300L-2 are arranged.

Further, in the example illustrated in FIG. 14, upper light-shielded,vertical 2-pixel-sharing focus detection pixels 300U-1 and 300U-2 andbottom light-shielded, vertical 2-pixel-sharing focus detection pixels300B-1 and 300B-2 are alternately arranged.

Namely, in the example illustrated in FIG. 14, left- andright-light-shielded and upper and bottom light-shielded focus detectionpixels are arranged in an intermingled manner.

Further, although FIG. 14 is illustrated as if there are focus detectionpixels consecutively arranged in the horizontal direction in thediagram, the focus detection pixels do not have to be consecutivelyarranged. For example, as illustrated in FIG. 4, ordinary imaging pixelsmay be arranged in between.

In addition, although ordinary imaging pixels are arranged in thevertical direction, left and right light-shielded and upper and bottomlight-shielded may be adjacent to each other.

FIGS. 15(A) to 15(D) are diagrams illustrating, for a 2-pixel-sharingcase, a fourth example of a light shielding pattern of the focusdetection pixels arranged in a pixel array portion as a fourthembodiment of the present technology.

This fourth example of light shielding is an example of slanted lightshielding.

FIG. 15(A) illustrates focus detection pixels 300LU-1 and 300LU-2 inwhich a left upper corner is shielded.

FIG. 15(B) illustrates focus detection pixels 300RU-1 and 300RU-2 inwhich a right upper corner is shielded.

FIG. 15(C) illustrates focus detection pixels 300LB-1 and 300LB-2 inwhich a left bottom corner is shielded.

FIG. 15(D) illustrates focus detection pixels 300RB-1 and 300RB-2 inwhich a right bottom corner is shielded.

FIG. 16 is a diagram illustrating, for a 4-pixel-sharing case, a firstexample of a light shielding pattern of the focus detection pixelsarranged in a pixel array portion as a fourth embodiment of the presenttechnology.

FIG. 16 illustrates an example in which left and right light-shieldedfocus detection pixels 300 are arranged on a part of a pixel arrayportion 1101.

In this example, left light-shielded, vertical 4-pixel-sharing focusdetection pixels 300L-1, 300L-2, 300L-2, and 300L-4 and rightlight-shielded, vertical 4-pixel-sharing focus detection pixels 300R-1,300R-2, 300R-2, and 300R-4 are arranged.

Further, although FIG. 16 is illustrated as if there are focus detectionpixels consecutively arranged in the horizontal direction in thediagram, the focus detection pixels do not have to be consecutivelyarranged. For example, as illustrated in FIG. 4, ordinary imaging pixelsmay be arranged in between.

FIG. 17 is a diagram illustrating, for a 4-pixel-sharing case, a secondexample of a light shielding pattern of the focus detection pixelsarranged in a pixel array portion as a fourth embodiment of the presenttechnology.

FIG. 17 illustrates an example in which upper and bottom light-shieldedfocus detection pixels 300 are arranged on a part of a pixel arrayportion 110J.

In this example, upper light-shielded, vertical 4-pixel-sharing focusdetection pixels 300U-1, 300U-2, 300U-3, and 300U-4 and bottomlight-shielded, vertical 4-pixel-sharing focus detection pixels 300B-1,300B-2, 300B-3, and 300B-4 are arranged.

Further, although FIG. 17 is illustrated as if there are focus detectionpixels consecutively arranged in the horizontal direction in thediagram, the focus detection pixels do not have to be consecutivelyarranged. For example, as illustrated in FIG. 4, ordinary imaging pixelsmay be arranged in between.

6. Fifth Embodiment

Next, a configuration example of focus detection pixels associated witha color filter will be described as a fifth embodiment.

Although in the following description an example is described using leftand right light-shielded focus detection pixels, the present technologycan be similarly applied to upper and bottom light shielding, slantedlight shielding and the like.

FIG. 18 is a diagram illustrating, for a 2-pixel-sharing case, anexample of a pixel array pattern in which there is no color filter inthe overall structure as a fifth embodiment of the present technology.

FIG. 18 illustrates an example in which upper and bottom light-shieldedfocus detection pixels 300 are arranged on a part of a pixel arrayportion 110K.

In this example, left light-shielded, vertical 2-pixel-sharing focusdetection pixels 300L-1 and 300L-2 and right light-shielded, vertical2-pixel-sharing focus detection pixels 300R-1 and 300R-2 are arranged.

FIG. 19 is a diagram illustrating, for a 2-pixel-sharing case, anexample of a pixel array pattern in which a color filter is provided inthe overall structure, but not for the focus detection pixels, as afifth embodiment of the present technology.

FIG. 19 illustrates an example in which, in an RGGB pixel Bayer array inwhich ordinary imaging pixels 200 are provided with a color filter CF, apixel array portion 110L is configured so that focus detection pixels300L-1, 300L-2, 300R-1, and 300R-2 are not provided with a color filter.

FIG. 20 is a diagram illustrating, for a 2-pixel-sharing case, anexample of a pixel array pattern in which a color filter is provided inthe overall structure, and is also provided for the focus detectionpixels, as a fifth embodiment of the present technology.

FIG. 20 illustrates an example in which, in an RGGB pixel Bayer array inwhich ordinary imaging pixels 200 are provided with a color filter CF, apixel array portion 110M is configured so that focus detection pixels300L-1, 300L-2, 300R-1, and 300R-2 are provided with a G color filter.

Note that the color filter CF provided for the focus detection pixelsmay be a R or a B color filter instead of G.

FIG. 21 is a diagram illustrating, for a 2-pixel-sharing case, anexample of a pixel array pattern in which a color filter is provided inthe overall structure, and is also provided for a part of the focusdetection pixels, as a fifth embodiment of the present technology.

FIG. 21 illustrates an example in which, in an RGGB pixel Bayer array inwhich ordinary imaging pixels 200 are provided with a color filter CF, apixel array portion 110N is configured so that focus detection pixels300L-1, 300L-2, 300R-1, and 300R-2 are partly provided with a G colorfilter. In this example, a color filter is provided for one of theshared pixels.

Note that the color filter CF provided for the focus detection pixelsmay be a R or a B color filter instead of G.

7. Sixth Embodiment

Next, a pixel arrangement example of horizontal 2-pixel-sharing will bedescribed as a sixth embodiment.

Although in the above first and third embodiments an example wasdescribed of a vertical 2-pixel-sharing type pixel array, in the sixthembodiment, an example of a horizontal 2-pixel-sharing type will bedescribed.

FIG. 22 is a diagram illustrating a first example of a horizontal2-pixel-sharing pixel array as a sixth embodiment of the presenttechnology.

Since the basic circuit configuration and the like are the same as forvertical pixel 2-pixel-sharing, a description thereof will be omittedhere.

The pixel array portion 110O illustrated in FIG. 22 is a 2×2 array, inwhich upper light shielding focus detection pixels 300U-1 and 300U-2 arearranged in a first row, second column, and bottom light shielding focusdetection pixels 300B-1 and 300B-2 are arranged in a second row, secondcolumn.

Further, the transfer gate electrode of the focus detection pixels300U-1 and 300U-2 are commonly connected to the transfer control lineLTR2, and the transfer gate electrode of the focus detection pixels300B-1 and 300B-2 are commonly connected to the transfer control lineLTR4.

In the following examples too, the transfer gate electrodes of the focusdetection pixels are connected to the transfer control lines LTR2 andLTR4.

FIG. 23 is a diagram illustrating a second example of a horizontal2-pixel-sharing pixel array as a sixth embodiment of the presenttechnology.

The pixel array portion 110P illustrated in FIG. 23 is a 2×2 array, inwhich right light shielding focus detection pixels 300R-1 and 300R-2 arearranged in a first row, second column, and left light shielding focusdetection pixels 300L-1 and 300L-2 are arranged in a second row, secondcolumn.

Further, the transfer gate electrode of the focus detection pixels300R-1 and 300R-2 are commonly connected to the transfer control lineLTR2, and the transfer gate electrode of the focus detection pixels300L-1 and 300L-2 are commonly connected to the transfer control lineLTR4.

In the following examples too, the transfer gate electrodes of the focusdetection pixels are connected to the transfer control lines LTR2 andLTR4.

FIG. 24 is a diagram illustrating a third example of a horizontal2-pixel-sharing pixel array as a sixth embodiment of the presenttechnology.

The pixel array portion 110Q illustrated in FIG. 24 is a 2×2 array, inwhich right light shielding focus detection pixels 300R-1 and 300R-2 arearranged in a first row, second column, and left light shielding focusdetection pixels 300L-1 and 300L-2 are arranged in a second row, secondcolumn.

Upper light shielding focus detection pixels 300U-1 and 300U-2 arearranged in a first row, fourth column, and bottom light shielding focusdetection pixels 300B-1 and 300B-2 are arranged in a second row, fourthcolumn.

Further, the transfer gate electrode of the focus detection pixels300R-1, 300R-2, 300U-1, and 300U-2 are commonly connected to thetransfer control line LTR2.

The transfer gate electrode of the focus detection pixels 300L-1,300L-2, 300B-1, and 300B-2 are commonly connected to the transfercontrol line LTR4.

Thus, in the example illustrated in FIG. 24, an array pattern isemployed in which left and right light-shielded and upper and bottomlight-shielded focus detection pixels are arranged in an intermingledmanner.

When looked at in a lateral (horizontal) direction, two focus detectionAF pixels are arranged alternating with (skipping two pixels) twoordinary pixels. However, ordinary pixels may be may be arranged inbetween focus detection pixels, or focus detection pixels may beconsecutively arranged.

Similarly, when looked at in a perpendicular (vertical) direction,although the focus detection pixels are arranged consecutively, aconsecutive arrangement is not necessary. For example, ordinary imagingpixels may be arranged between focus detection pixels.

FIG. 25 is a diagram illustrating a fourth example of a horizontal2-pixel-sharing pixel array as a sixth embodiment of the presenttechnology.

The pixel array portion 110R illustrated in FIG. 25 employs an arraypattern in which left and right light-shielded and upper and bottomlight-shielded focus detection pixels are arranged consecutively.

A detailed description of this array pattern will be omitted.

FIGS. 26(A) to 26(D) are diagrams illustrating, for a horizontal2-pixel-sharing case, an example of a light shielding pattern of thefocus detection pixels arranged in a pixel array portion as a sixthembodiment of the present technology.

FIG. 26 illustrates an example of slanted light shielding.

FIG. 26(A) illustrates focus detection pixels 300LU-1 and 300LU-2 inwhich a left upper corner is shielded.

FIG. 26(B) illustrates focus detection pixels 300RU-1 and 300RU-2 inwhich a right upper corner is shielded.

FIG. 26(C) illustrates focus detection pixels 300LB-1 and 300LB-2 inwhich a left bottom corner is shielded.

FIG. 26(D) illustrates focus detection pixels 300RB-1 and 300RB-2 inwhich a right bottom corner is shielded.

As described above, according to an embodiment of the presenttechnology, the following advantageous effects can be obtained.

According to an embodiment of the present technology, since accumulatedsignals from the focus detection pixels sharing a floating diffusionlayer FD are subjected to FD addition, the signal level (sensitivity) ofthe focus detection pixels improves, so that focus detection accuracyduring low illumination is improved.

The PD characteristics (Qs etc.) of the focus detection pixels can bethe same as those of the ordinary imaging pixels.

Further, miniaturization of the photoelectric conversion unit (PD) isbetter than in the related-art examples, the ordinary imaging pixels andthe focus detection pixels can be configured with the same potentialdesign, and lower costs can be achieved.

In addition, according to an embodiment of the present technology, sincesignals can be added by the FD layer due to electrical sharing of thetransfer gates in the pixel array portion, twice as many signals thanpreviously can be obtained, so that the sensitivity (phase differenceaccuracy) of the focus detection pixels improves.

Therefore, the need to incorporate a special potential for the focusdetection pixels is eliminated, so that the incorporation of a potentialfor the focus detection pixels can be carried out in the same manner asfor the ordinary imaging pixels.

A solid-state image sensor having such advantageous effects can beapplied as an imaging device in a digital camera or a video camera.

8. Configuration Example of a Camera System

FIG. 27 is a diagram illustrating an example of a configuration of acamera system in which the solid-state image sensor according to anembodiment of the present technology is applied.

As illustrated in FIG. 27, a camera system 400 has an imaging device 410that can apply the solid-state image sensor 100 according to anembodiment of the present technology.

Further, the camera system 400 has an optical system that guides lightincident on a pixel area of the imaging device 410 (forms an image of anobject image), for example a lens 420 that forms an image on an imagingplane from incident light (image light).

The camera system 400 has a drive circuit (DRV) 430 for driving theimaging device 410 and a signal processing circuit (PRC) 440 forprocessing output signals from the imaging device 410.

The drive circuit 430 has a timing generator (not illustrated) thatgenerates various timing signals including a start pulse and a clockpulse for driving the circuits in the imaging device 410. The drivecircuit 430 drives the imaging device 410 based on a predeterminedtiming signal.

Further, the signal processing circuit 440 performs predetermined signalprocessing on the output signals from the imaging device 410.

For example, by carrying out image deviation detection and calculationprocessing (correlation calculation processing, phase differencedetection processing) with the signal processing circuit 440, the amountof image deviation between a pair of images is detected based on aso-called pupil division phase difference detection method.

Further, the deviation (defocus amount) of the current image formingplane (the image forming plane at the focus detection positioncorresponding to the position of the microlens array on the expectedimage forming plane) with respect to the expected image forming plane iscalculated by performing conversion and calculation based on a centroidinterval of a pair of focus pupils on the image deviation amount.

The image signals processed by the signal processing circuit 440 arerecorded on a recording medium such as a memory. The image informationrecorded on the recording medium is produced as a hard copy by printing,for example. Further, the image signals processed by the signalprocessing circuit 440 are displayed as moving images on a monitorconfigured from a liquid crystal display, for example.

As described above, a low power consumption, high accuracy camera can berealized by mounting the above-described solid-state image sensor 100 asan imaging device 410 in an imaging apparatus, such as a digital camera.

Additionally, the present technology may also be configured as below.

(1) A solid-state image sensor including:

a pixel array portion formed from a two-dimensional array of ordinaryimaging pixels each having a photoelectric conversion unit andconfigured to output an electric signal obtained through photoelectricconversion as a pixel signal, and focus detection pixels for detectingfocus,

wherein the focus detection pixels include at least a first focusdetection pixel and a second focus detection pixel each having aphotoelectric conversion unit and configured to transfer and output anelectric signal obtained through photoelectric conversion to an outputnode,

wherein the first focus detection pixel and the second focus detectionpixel share the output node,

wherein the first focus detection pixel includes

-   -   a first photoelectric conversion unit, and    -   a first transfer gate for reading out an electron generated        through photoelectric conversion in the first photoelectric        conversion unit to the shared output node,

wherein the second focus detection pixel includes

-   -   a second photoelectric conversion unit, and    -   a second transfer gate for reading out an electron generated        through photoelectric conversion in the second photoelectric        conversion unit to the shared output node, and

wherein the first transfer gate of the first focus detection pixel andthe second transfer gate of the second focus detection pixel areelectrically shared by a gate electrode to which a control signal forconduction control is applied.

(2) The solid-state image sensor according to (1),

wherein the ordinary imaging pixels share, with at least two pixels, anoutput node to which an electron generated through photoelectricconversion is transferred,

wherein the ordinary imaging pixels each have transfer gates such thatthe two pixels transfer to the shared output node,

wherein each of the transfer gates is subjected to conduction control byan individual transfer control signal, and

wherein the first transfer gate of the first focus detection pixel andthe second transfer gate of the second focus detection pixel aresubjected to conduction control concurrently and in parallel by thetransfer control signal.

(3) The solid-state image sensor according to (1) or (2), wherein atleast one edge of the focus detection pixel for detecting focus and atleast one edge of the ordinary imaging pixel are adjacent.

(4) The solid-state image sensor according to any one of (1) to (3),wherein the first focus detection pixel and the second focus detectionpixel have parts of light incident areas shielded at which light isincident on the photoelectric conversion units.

(5) The solid-state image sensor according to any one of (1) to (4),wherein the first focus detection pixel and the second focus detectionpixel have a same aperture size.

(6) The solid-state image sensor according to any one of (1) to (5),wherein the ordinary imaging pixels have a larger aperture size than anaperture size of the focus detection pixels.

(7) The solid-state image sensor according to any one of (1) to (6),wherein the focus detection pixels include a pixel for which a colorfilter is not provided.

(8) The solid-state image sensor according to any one of (1) to (6),

wherein the pixel array portion is provided with a color filter, and

wherein a color filter is not provided for one of the first focusdetection pixel or the second focus detection pixel.

(9) The solid-state image sensor according to any one of (1) to (6),

wherein the pixel array portion is provided with a color filter, and

wherein color filters having a same color are provided for the firstfocus detection pixel and the second focus detection pixel.

(10) The solid-state image sensor according to any one of (1) to (9),wherein the focus detection pixels for detecting focus and the ordinaryimaging pixels have a same pixel size.

(11) The solid-state image sensor according to any one of (1) to (10),wherein the focus detection pixels sharing the output node include twoor more pixels.

(12) A camera system including:

a solid-state image sensor;

an optical unit configured to form an image of an object image on thesolid-state image sensor; and

a signal processing unit configured to process an output signal from thesolid-state image sensor,

the solid-state image sensor including a pixel array portion formed froma two-dimensional array of ordinary imaging pixels each having aphotoelectric conversion unit and configured to output an electricsignal obtained through photoelectric conversion as a pixel signal, andfocus detection pixels for detecting focus,

wherein the focus detection pixels include at least a first focusdetection pixel and a second focus detection pixel each having aphotoelectric conversion unit and configured to transfer and output anelectric signal obtained through photoelectric conversion to an outputnode,

wherein the first focus detection pixel and the second focus detectionpixel share the output node,

wherein the first focus detection pixel includes

-   -   a first photoelectric conversion unit, and    -   a first transfer gate for reading out an electron generated        through photoelectric conversion in the first photoelectric        conversion unit to the shared output node,

wherein the second focus detection pixel includes

-   -   a second photoelectric conversion unit, and    -   a second transfer gate for reading out an electron generated        through photoelectric conversion in the second photoelectric        conversion unit to the shared output node, and

wherein the first transfer gate of the first focus detection pixel andthe second transfer gate of the second focus detection pixel areelectrically shared by a gate electrode to which a control signal forconduction control is applied.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

The present disclosure contains subject matter related to that disclosedin Japanese Priority Patent Application JP 2012-018383 filed in theJapan Patent Office on Jan. 31, 2012, the entire content of which ishereby incorporated by reference.

What is claimed is:
 1. An image sensor comprising a plurality of focusdetection pixels for detecting focus, at least one of the focusdetection pixels including: a floating diffusion region formed in asubstrate; a first photoelectric conversion region; a first transfertransistor disposed between the first photoelectric conversion regionand the floating diffusion region; a second photoelectric conversionregion; and a second transfer transistor disposed between the secondphotoelectric conversion region and the floating diffusion region,wherein, a gate of the first transfer transistor and a gate of thesecond transfer transistor are electrically connected to a control linethrough a connection wiring having “]” shape in a plan view, theconnection wiring is formed in a first metal layer, the control line isformed in a second metal layer, and the first metal layer is disposedbetween the second metal layer and the substrate.
 2. The image sensoraccording to claim 1, wherein a part of the first photoelectricconversion region and the second photoelectric conversion region isshielded from incident light.
 3. The image sensor according to claim 1,wherein the focus detection pixels include a pixel for which a colorfilter is not provided.
 4. A camera system comprising the image sensoraccording to claim 1.